Leakage compensation circuit for phase-locked loop (pll) large thin oxide capacitors

ABSTRACT

Certain aspects of the present disclosure provide methods and apparatus for compensating, or at least adjusting, for capacitor leakage. One example method generally includes determining a leakage voltage corresponding to a leakage current of a capacitor in a filter for a phase-locked loop (PLL), wherein the determining comprises closing a set of switches for discontinuous sampling of the leakage voltage; based on the sampled leakage voltage, generating a sourced current approximately equal to the leakage current; and injecting the sourced current into the capacitor.

CLAIM OF PRIORITY UNDER 35 U.S.C. §119

The present application is a continuation of U.S. patent applicationSer. No. 14/743,360, filed Jun. 18, 2015 and entitled “LEAKAGECOMPENSATION CIRCUIT FOR PHASE-LOCKED LOOP (PLL) LARGE THIN OXIDECAPACITORS,” which claims benefit of U.S. Provisional Patent ApplicationSer. No. 62/121,588, entitled “LEAKAGE COMPENSATION CIRCUIT FORPHASE-LOCKED LOOP (PLL) LARGE THIN OXIDE CAPACITORS” and filed Feb. 27,2015, which are both assigned to the assignee of the present applicationand hereby expressly incorporated by reference herein in theirentireties.

TECHNICAL FIELD

Certain aspects of the present disclosure generally relate to radiofrequency (RF) circuits and, more particularly, to leakage currentcompensation, or at least adjustment, for capacitors in phase-lockedloop (PLL) circuits.

BACKGROUND

Wireless communication networks are widely deployed to provide variouscommunication services such as telephony, video, data, messaging,broadcasts, and so on. Such networks, which are usually multiple accessnetworks, support communications for multiple users by sharing theavailable network resources. For example, one network may be a 3G (thethird generation of mobile phone standards and technology) system, whichmay provide network service via any one of various 3G radio accesstechnologies (RATs) including EVDO (Evolution-Data Optimized), 1×RTT (1times Radio Transmission Technology, or simply 1×), W-CDMA (WidebandCode Division Multiple Access), UMTS-TDD (Universal MobileTelecommunications System-Time Division Duplexing), HSPA (High SpeedPacket Access), GPRS (General Packet Radio Service), or EDGE (EnhancedData rates for Global Evolution). The 3G network is a wide area cellulartelephone network that evolved to incorporate high-speed internet accessand video telephony, in addition to voice calls. Furthermore, a 3Gnetwork may be more established and provide larger coverage areas thanother network systems. Such multiple access networks may also includecode division multiple access (CDMA) systems, time division multipleaccess (TDMA) systems, frequency division multiple access (FDMA)systems, orthogonal frequency division multiple access (OFDMA) systems,single-carrier FDMA (SC-FDMA) networks, 3^(rd) Generation PartnershipProject (3GPP) Long Term Evolution (LTE) networks, and Long TermEvolution Advanced (LTE-A) networks.

A wireless communication network may include a number of base stationsthat can support communication for a number of mobile stations. A mobilestation (MS) may communicate with a base station (BS) via a downlink andan uplink. The downlink (or forward link) refers to the communicationlink from the base station to the mobile station, and the uplink (orreverse link) refers to the communication link from the mobile stationto the base station. A base station may transmit data and controlinformation on the downlink to a mobile station and/or may receive dataand control information on the uplink from the mobile station.

SUMMARY

Certain aspects of the present disclosure generally relate to leakagecurrent compensation, or at least adjustment, for a filter capacitor ina phase-locked loop (PLL), for example.

Certain aspects of the present disclosure provide a method for capacitorleakage current adjustment. The method generally includes sensing, withan amplifier, a first leakage current of a first capacitor in a filterfor a PLL, or a second leakage current of a second capacitorrepresentative of the first capacitor; controlling a current source withthe amplifier based on the sensed first or second leakage current, suchthat a sourced current generated by the current source is approximatelyequal to the first leakage current; and injecting the sourced currentinto the first capacitor.

Certain aspects of the present disclosure provide a method for capacitorleakage current adjustment. The method generally includes sampling afirst leakage current of a first capacitor in a filter for a PLL, or asecond leakage current of a second capacitor representative of the firstcapacitor, wherein the sampling comprises closing a first set ofswitches for discontinuous sampling of the first or second leakagecurrent; controlling a current source with an amplifier based on thesampled first or second leakage current, such that a sourced currentgenerated by the current source is approximately equal to the firstleakage current; and injecting the sourced current into the firstcapacitor.

Certain aspects of the present disclosure provide a method for capacitorleakage current adjustment. The method generally includes determining aleakage voltage based on a leakage current of a capacitor in a filterfor a PLL, wherein the determining comprises closing a set of switchesfor discontinuous sampling of the leakage voltage; based on the sampledleakage voltage, generating a sourced current approximately equal to theleakage current; and injecting the sourced current into the capacitor.

Certain aspects of the present disclosure provide a circuit. The circuitgenerally includes a filter for a PLL comprising a first capacitor; anamplifier configured to sense a first leakage current of the firstcapacitor, or a second leakage current of a second capacitorrepresentative of the first capacitor; and a current source configuredto generate a sourced current for injection into the first capacitor,wherein the amplifier is configured to control the current source basedon the sensed first or second leakage current such that the sourcedcurrent is approximately equal to the first leakage current.

Certain aspects of the present disclosure provide a circuit. The circuitgenerally includes a filter for a PLL comprising a first capacitor; afirst set of switches configured to be closed for the circuit to samplea first leakage current of the first capacitor, or a second leakagecurrent of a second capacitor representative of the first capacitor; acurrent source configured to generate a sourced current for injectioninto the first capacitor, and an amplifier configured to control thecurrent source based on the sampled first or second leakage current suchthat the sourced current is approximately equal to the first leakagecurrent.

Certain aspects of the present disclosure provide a circuit. The circuitgenerally includes a filter for a PLL comprising a capacitor; a set ofswitches configured to be closed for the circuit to sample a leakagevoltage based on a leakage current of the capacitor; a current sourceconfigured to generate a sourced current for injection into thecapacitor; and an amplifier configured to control the current sourcebased on the sampled leakage voltage such that the sourced current isapproximately equal to the leakage current.

According to certain aspects, the capacitor comprises a thin oxidecapacitor.

According to certain aspects, the sourced current is injected into thecapacitor such that a voltage drop across a resistor in series with thecapacitor is approximately zero volts. In certain aspects, the circuitfurther includes a charge pump for the PLL. In this case, a first end ofthe capacitor may be coupled to a reference node for the filter, asecond end of the capacitor may be coupled to a first end of theresistor and to the current source, and a second end of the resistor maybe coupled to the charge pump.

According to certain aspects, the circuit further includes a samplingcapacitor. In this case, the set of switches may be configured to beclosed for the circuit to store the leakage voltage across the samplingcapacitor and to short first and second inputs of the amplifier to acommon-mode voltage of the filter. In certain aspects, the circuitfurther includes another set of switches. In this case, the currentsource may comprise a transistor, and the other set of switches may beconfigured to be closed for the circuit to sense the leakage voltagestored across the sampling capacitor with the first and second inputs ofthe amplifier and to connect an output of the amplifier with a gate ofthe transistor. In certain aspects, the circuit further includes acharge pump for the PLL. In this case, the set of switches may be closedif the charge pump is inactive. In certain aspects, the other set ofswitches is closed if the charge pump is active. In certain aspects, thecircuit further includes another capacitor connected between a sourceand a gate of the transistor and configured to maintain a gate-to-sourcevoltage of the transistor if the other set of switches is open. Incertain aspects, the capacitor may be a thin oxide capacitor, and thesampling capacitor may be a thick oxide capacitor.

According to certain aspects, the circuit further includes anothercapacitor having a leakage current proportional to the leakage currentof the capacitor in the filter, wherein the other capacitor is coupledto the a first input of the amplifier, a sampling capacitor coupled to asecond input of the amplifier, and a voltage follower configured tobuffer the leakage voltage. In this case, the set of switches may beconfigured to be closed for the circuit to store the buffered leakagevoltage across the other capacitor and across the sampling capacitor.For certain aspects, the current source may comprise a first transistor,the other capacitor may be the same capacitor type as the capacitor inthe filter, the first input of the amplifier may be coupled to the othercapacitor and to a drain of a second transistor, an output of theamplifier may be coupled to a gate of the second transistor, and acapacitance ratio of the capacitor in the filter to the other capacitormay be equal to a size ratio of the first transistor to the secondtransistor. In certain aspects, the circuit further includes another setof switches configured, if closed, to connect the output of theamplifier with a gate of the first transistor. In certain aspects, theother set of switches is configured, if opened, to disconnect the outputof the amplifier from the gate of the first transistor, and the set ofswitches is configured, if opened, to disconnect an output of thevoltage follower from the other capacitor and from the samplingcapacitor. In certain aspects, the circuit further includes a chargepump for the PLL. In this case, the set of switches may be closed if thecharge pump is inactive, and the other set of switches may be closed ifthe charge pump is active. In certain aspects, the circuit furtherincludes yet another capacitor connected between a source and a gate ofthe first transistor to maintain a gate-to-source voltage of the firsttransistor if the other set of switches is open. In certain aspects, thecapacitor in the filter and the other capacitor may be thin oxidecapacitors, and the sampling capacitor may be a thick oxide capacitor.

Certain aspects of the present disclosure provide an apparatus. Theapparatus generally includes means for determining a leakage voltagebased on a leakage current of a capacitor in a filter for a PLL, whereinthe means for determining is configured to close a set of switches fordiscontinuous sampling of the leakage voltage; means for sourcingcurrent; means for controlling the means for sourcing current based onthe sampled leakage voltage, such that the sourced current isapproximately equal to the leakage current; and means for injecting thesourced current into the capacitor.

BRIEF DESCRIPTION OF THE DRAWINGS

So that the manner in which the above-recited features of the presentdisclosure can be understood in detail, a more particular description,briefly summarized above, may be had by reference to aspects, some ofwhich are illustrated in the appended drawings. It is to be noted,however, that the appended drawings illustrate only certain typicalaspects of this disclosure and are therefore not to be consideredlimiting of its scope, for the description may admit to other equallyeffective aspects.

FIG. 1 is a diagram of an example wireless communications network inaccordance with certain aspects of the present disclosure.

FIG. 2 is a block diagram of an example access point (AP) and exampleuser terminals in accordance with certain aspects of the presentdisclosure.

FIG. 3 is a block diagram of an example transceiver front end inaccordance with certain aspects of the present disclosure.

FIG. 4 is a circuit diagram of an example leakage compensation circuitoperable during a phase-locked loop (PLL) lock condition, in accordancewith certain aspects of the present disclosure.

FIG. 5 is a circuit diagram of an example leakage compensation circuitcomprising switches for sampling a leakage current during a sensing modeand injecting an equivalent leakage current during an action mode, inaccordance with certain aspects of the present disclosure.

FIG. 6 is a circuit diagram of an example circuit for compensating forleakage of a filter capacitor using a representative capacitor having aleakage current that is proportional to the leakage of the filtercapacitor, in accordance with certain aspects of the present disclosure.

FIG. 7 is a circuit diagram of an example circuit for compensating forleakage of a filter capacitor using a sampling capacitor, a buffer, anda representative capacitor having a leakage current that is proportionalto the leakage of the filter capacitor, in accordance with certainaspects of the present disclosure.

FIG. 8 is a flow diagram of example operations for compensating, or atleast adjusting, for capacitor leakage, in accordance with certainaspects of the present disclosure.

DETAILED DESCRIPTION

Various aspects of the present disclosure are described below. It shouldbe apparent that the teachings herein may be embodied in a wide varietyof forms and that any specific structure, function, or both beingdisclosed herein is merely representative. Based on the teachingsherein, one skilled in the art should appreciate that an aspectdisclosed herein may be implemented independently of any other aspectsand that two or more of these aspects may be combined in various ways.For example, an apparatus may be implemented or a method may bepracticed using any number of the aspects set forth herein. In addition,such an apparatus may be implemented or such a method may be practicedusing other structure, functionality, or structure and functionality inaddition to or other than one or more of the aspects set forth herein.Furthermore, an aspect may comprise at least one element of a claim.

The word “exemplary” is used herein to mean “serving as an example,instance, or illustration.” Any aspect described herein as “exemplary”is not necessarily to be construed as preferred or advantageous overother aspects.

The techniques described herein may be used in combination with variouswireless technologies such as Code Division Multiple Access (CDMA),Orthogonal Frequency Division Multiplexing (OFDM), Time DivisionMultiple Access (TDMA), Spatial Division Multiple Access (SDMA), SingleCarrier Frequency Division Multiple Access (SC-FDMA), Time DivisionSynchronous Code Division Multiple Access (TD-SCDMA), and so on.Multiple user terminals can concurrently transmit/receive data viadifferent (1) orthogonal code channels for CDMA, (2) time slots forTDMA, or (3) sub-bands for OFDM. A CDMA system may implement IS-2000,IS-95, IS-856, Wideband-CDMA (W-CDMA), or some other standards. An OFDMsystem may implement Institute of Electrical and Electronics Engineers(IEEE) 802.11, IEEE 802.16, Long Term Evolution (LTE) (e.g., in TDDand/or FDD modes), or some other standards. A TDMA system may implementGlobal System for Mobile Communications (GSM) or some other standards.These various standards are known in the art.

An Example Wireless System

FIG. 1 illustrates a wireless communications system 100 with accesspoints 110 and user terminals 120. For simplicity, only one access point110 is shown in FIG. 1. An access point (AP) is generally a fixedstation that communicates with the user terminals and may also bereferred to as a base station (BS), an evolved Node B (eNB), or someother terminology. A user terminal (UT) may be fixed or mobile and mayalso be referred to as a mobile station (MS), an access terminal, userequipment (UE), a station (STA), a client, a wireless device, or someother terminology. A user terminal may be a wireless device, such as acellular phone, a personal digital assistant (PDA), a handheld device, awireless modem, a laptop computer, a tablet, a personal computer, etc.

Access point 110 may communicate with one or more user terminals 120 atany given moment on the downlink and uplink. The downlink (i.e., forwardlink) is the communication link from the access point to the userterminals, and the uplink (i.e., reverse link) is the communication linkfrom the user terminals to the access point. A user terminal may alsocommunicate peer-to-peer with another user terminal. A system controller130 couples to and provides coordination and control for the accesspoints.

System 100 employs multiple transmit and multiple receive antennas fordata transmission on the downlink and uplink. Access point 110 may beequipped with a number N_(ap) of antennas to achieve transmit diversityfor downlink transmissions and/or receive diversity for uplinktransmissions. A set N_(u) of selected user terminals 120 may receivedownlink transmissions and transmit uplink transmissions. Each selecteduser terminal transmits user-specific data to and/or receivesuser-specific data from the access point. In general, each selected userterminal may be equipped with one or multiple antennas (i.e., N_(ut)≧1).The N_(u) selected user terminals can have the same or different numberof antennas.

Wireless system 100 may be a time division duplex (TDD) system or afrequency division duplex (FDD) system. For a TDD system, the downlinkand uplink share the same frequency band. For an FDD system, thedownlink and uplink use different frequency bands. System 100 may alsoutilize a single carrier or multiple carriers for transmission. Eachuser terminal 120 may be equipped with a single antenna (e.g., in orderto keep costs down) or multiple antennas (e.g., where the additionalcost can be supported).

FIG. 2 shows a block diagram of access point 110 and two user terminals120 m and 120 x in wireless system 100. Access point 110 is equippedwith N_(ap) antennas 224 a through 224 ap. User terminal 120 m isequipped with N_(ut,m) antennas 252 ma through 252 mu, and user terminal120 x is equipped with N_(ut,x) antennas 252 xa through 252 xu. Accesspoint 110 is a transmitting entity for the downlink and a receivingentity for the uplink. Each user terminal 120 is a transmitting entityfor the uplink and a receiving entity for the downlink. As used herein,a “transmitting entity” is an independently operated apparatus or devicecapable of transmitting data via a frequency channel, and a “receivingentity” is an independently operated apparatus or device capable ofreceiving data via a frequency channel. In the following description,the subscript “dn” denotes the downlink, the subscript “up” denotes theuplink, N_(up) user terminals are selected for simultaneous transmissionon the uplink, N_(dn) user terminals are selected for simultaneoustransmission on the downlink, N_(up) may or may not be equal to N_(dn),and N_(up) and N_(dn) may be static values or can change for eachscheduling interval. Beam-steering or some other spatial processingtechnique may be used at the access point and user terminal.

On the uplink, at each user terminal 120 selected for uplinktransmission, a TX data processor 288 receives traffic data from a datasource 286 and control data from a controller 280. TX data processor 288processes (e.g., encodes, interleaves, and modulates) the traffic data{d_(up)} for the user terminal based on the coding and modulationschemes associated with the rate selected for the user terminal andprovides a data symbol stream {s_(up)} for one of the N_(ut,m) antennas.A transceiver front end (TX/RX) 254 (also known as a radio frequencyfront end (RFFE)) receives and processes (e.g., converts to analog,amplifies, filters, and frequency upconverts) a respective symbol streamto generate an uplink signal. The transceiver front end 254 may alsoroute the uplink signal to one of the N_(ut,m) antennas for transmitdiversity via an RF switch, for example. The controller 280 may controlthe routing within the transceiver front end 254. Memory 282 may storedata and program codes for the user terminal 120 and may interface withthe controller 280.

A number N_(up) of user terminals 120 may be scheduled for simultaneoustransmission on the uplink. Each of these user terminals transmits itsset of processed symbol streams on the uplink to the access point.

At access point 110, N_(ap) antennas 224 a through 224 ap receive theuplink signals from all N_(up) user terminals transmitting on theuplink. For receive diversity, a transceiver front end 222 may selectsignals received from one of the antennas 224 for processing. The accesspoint's transceiver front end 222 also performs processing complementaryto that performed by the user terminal's transceiver front end 254 andprovides a recovered uplink data symbol stream. The recovered uplinkdata symbol stream is an estimate of a data symbol stream {s_(up)}transmitted by a user terminal. An RX data processor 242 processes(e.g., demodulates, deinterleaves, and decodes) the recovered uplinkdata symbol stream in accordance with the rate used for that stream toobtain decoded data. The decoded data for each user terminal may beprovided to a data sink 244 for storage and/or a controller 230 forfurther processing.

On the downlink, at access point 110, a TX data processor 210 receivestraffic data from a data source 208 for N_(dn) user terminals scheduledfor downlink transmission, control data from a controller 230 andpossibly other data from a scheduler 234. The various types of data maybe sent on different transport channels. TX data processor 210 processes(e.g., encodes, interleaves, and modulates) the traffic data for eachuser terminal based on the rate selected for that user terminal. TX dataprocessor 210 may provide a downlink data symbol streams for one of moreof the N_(dn) user terminals to be transmitted from one of the N_(ap)antennas. The transceiver front end 222 receives and processes (e.g.,converts to analog, amplifies, filters, and frequency upconverts) thesymbol stream to generate a downlink signal. The transceiver front end222 may also route the downlink signal to one or more of the N_(ap)antennas 224 for transmit diversity via an RF switch, for example. Thecontroller 230 may control the routing within the transceiver front end222. Memory 232 may store data and program codes for the access point110 and may interface with the controller 230

At each user terminal 120, N_(ut,m) antennas 252 receive the downlinksignals from access point 110. For receive diversity at the userterminal 120, the transceiver front end 254 may select signals receivedfrom one of the antennas 252 for processing. The user terminal'stransceiver front end 254 also performs processing complementary to thatperformed by the access point's transceiver front end 222 and provides arecovered downlink data symbol stream. An RX data processor 270processes (e.g., demodulates, deinterleaves, and decodes) the recovereddownlink data symbol stream to obtain decoded data for the userterminal.

Those skilled in the art will recognize the techniques described hereinmay be generally applied in systems utilizing any type of multipleaccess schemes, such as TDMA, SDMA, Orthogonal Frequency DivisionMultiple Access (OFDMA), CDMA, SC-FDMA, TD-SCDMA, and combinationsthereof.

FIG. 3 is a block diagram of an example transceiver front end 300, suchas transceiver front ends 222, 254 in FIG. 2, in accordance with certainaspects of the present disclosure. The transceiver front end 300includes a transmit (TX) path 302 (also known as a transmit chain) fortransmitting signals via one or more antennas and a receive (RX) path304 (also known as a receive chain) for receiving signals via theantennas. When the TX path 302 and the RX path 304 share an antenna 303,the paths may be connected with the antenna via an interface 306, whichmay include any of various suitable RF devices, such as a duplexer, aswitch, a diplexer, and the like.

Receiving in-phase (I) or quadrature (Q) baseband analog signals from adigital-to-analog converter (DAC) 308, the TX path 302 may include abaseband filter (BBF) 310, a mixer 312, a driver amplifier (DA) 314, anda power amplifier 316. The BBF 310, the mixer 312, and the DA 314 may beincluded in a radio frequency integrated circuit (RFIC), while the PA316 is often external to the RFIC. The BBF 310 filters the basebandsignals received from the DAC 308, and the mixer 312 mixes the filteredbaseband signals with a transmit local oscillator (LO) signal to convertthe baseband signal of interest to a different frequency (e.g.,upconvert from baseband to RF). Known as heterodyning, this frequencyconversion process produces the sum and difference frequencies of the LOfrequency and the frequency of the signal of interest. The sum anddifference frequencies are referred to as the beat frequencies. The beatfrequencies are typically in the RF range, such that the signals outputby the mixer 312 are typically RF signals, which are amplified by the DA314 and by the PA 316 before transmission by the antenna 303.

The RX path 304 includes a low noise amplifier (LNA) 322, a mixer 324,and a baseband filter (BBF) 326. The LNA 322, the mixer 324, and the BBF326 may be included in a radio frequency integrated circuit (RFIC),which may or may not be the same RFIC that includes the TX pathcomponents. RF signals received via the antenna 303 may be amplified bythe LNA 322, and the mixer 324 mixes the amplified RF signals with areceive local oscillator (LO) signal to convert the RF signal ofinterest to a different baseband frequency (i.e., downconvert). Thebaseband signals output by the mixer 324 may be filtered by the BBF 326before being converted by an analog-to-digital converter (ADC) 328 todigital I or Q signals for digital signal processing.

While it is desirable for the output of an LO to remain stable infrequency, tuning to different frequencies indicates using avariable-frequency oscillator, which involves compromises betweenstability and tunability. Contemporary systems may employ frequencysynthesizers with a voltage-controlled oscillator (VCO) (e.g., in aphase-locked loop (PLL)) to generate a stable, tunable LO with aparticular tuning range. Thus, the transmit LO is typically produced bya TX frequency synthesizer 318, which may be buffered or amplified byamplifier 320 before being mixed with the baseband signals in the mixer312. Similarly, the receive LO is typically produced by an RX frequencysynthesizer 330, which may be buffered or amplified by amplifier 332before being mixed with the RF signals in the mixer 324.

Example Leakage Compensation Circuit

Thick oxide capacitors have been used in complementarymetal-oxide-semiconductor (CMOS) design for filters, such as charge pumpfilters in phase-locked loop (PLL) circuits. However, thin layer metaloxide semiconductor (MOS) capacitors (a.k.a. thin oxide capacitors) mayhave greater density than thick oxide capacitors. For example, thedensity of thick oxide capacitors may be less than half that of thinoxide capacitors. The trend towards reducing chip area and saving moresilicon (Si) has motivated replacing thick oxide capacitors with thinoxide capacitors.

Filters used in PLL circuits typically use bulky capacitors on the orderof a few hundred picofarads, which take up a large amount of area in aPLL. However, the leakage current (or “leakage” for short) of thin oxidecapacitors may be greater than that of thick oxide capacitors and, thus,may be problematic in many applications. For example, the leakage ofthin oxide capacitors may be an issue for PLL filters. The leakagecurrent of thin oxide capacitors may be more problematic in low powerPLL designs (e.g., Bluetooth (BT) and frequency modulation (FM)) inwhich the capacitor leakage current is comparable with the PLL chargepump current. In addition, the leakage current of a thin oxide capacitormay be highly dependent on process, voltage, and temperature (PVT). Forexample, the voltage dependency of the leakage may cause severenonlinearity in the PLL dynamic behavior.

Therefore, what is needed are apparatus and techniques for compensatingfor the leakage current of a thin oxide capacitor in PLL circuits.Aspects of the present disclosure provide feedback techniques that senseand compensate, or at least adjust, for this leakage current (e.g., byre-injecting current approximately equal to the leakage current backinto the thin oxide capacitor). In certain aspects, the method ofsensing the leakage current differentiates between filter capacitorleakage current and charge pump current.

FIG. 4 is a circuit diagram of an example circuit 400 for leakagecurrent cancellation (e.g., compensation) during a PLL lock condition(i.e., when the PLL is locked in phase), in accordance with certainaspects of the present disclosure. The circuit 400 comprises a chargepump 402, a low pass filter (LPF) 404, and leakage circuitry 406. Theleakage circuitry 406 may be configured to compensate for leakagecurrent across a thin oxide capacitor C_(Z) (e.g., the capacitor Cz maybe a filter capacitor connected in series with a resistor Rz as shown).

An amplifier 408 of the leakage circuitry 406 senses a voltagerepresentative of the leakage current across the capacitor Cz while thePLL is locked (e.g., the charge pump 402 is off). During the PLL lockduration, a voltage VC1 at an input of the LPF 404 may be equal to avoltage VC2 (e.g., tuning voltage (Vtune) for the VCO) at an output ofthe LPF 404 because the charge pump 402 may not be driving any (or verylittle) current across a resistor R1 in the LPF. Therefore, thedifferential input of the amplifier 408 effectively senses the voltageacross the resistor Rz, which is representative of the leakage currentof the capacitor Cz. That is, the leakage current across the capacitorCz results in a differential voltage across the positive and negativeterminals of the amplifier 408, which drives the gate of a PMOStransistor M1.

The transistor M1 compensates for the leakage current of the capacitorCz by supplying (e.g., injecting) a current from power supply railV_(DD) to the capacitor Cz, based on the leakage current sensed by theamplifier 408. For example, the transistor M1 compensates for theleakage current of the capacitor Cz such that no voltage drop is sensedby the amplifier 408 across the resistor Rz (e.g., none of the leakagecurrent of capacitor Cz is flowing across the resistor Rz).

FIG. 5 is a circuit diagram of an example circuit 500 for leakagecurrent compensation that may operate regardless of whether the PLL islocked (e.g., charge pump is active or inactive), in accordance withcertain aspects of the present disclosure. The circuit 500 comprises thecharge pump 402, the LPF 404, and leakage circuitry 502. The leakagecircuitry 502 comprises a sampling capacitor Cs, which may be a thickoxide capacitor having a substantially lower leakage current thancapacitor Cz. During a lock condition of the PLL (e.g., charge pump isoff), switches Φ₁ are closed, and switches Φ_(1B) are open (which may bereferred to as the “sensing mode”). Therefore, the sampling capacitor Csis connected in parallel to resistor Rz. Thus, the voltage acrossresistor Rz (e.g., due to the leakage current of capacitor Cz) will bestored on the sampling capacitor Cs during the sensing mode. This allowsfor the leakage current to be sensed independent of the chargetransferred by the charge pump because the charge pump is off during thesensing mode.

When the PLL is not locked (e.g., charge pump is on), switches Φ₁ areopened, and switches Φ_(1B) are closed (which may be referred to as the“action mode”). Thus, the sampling capacitor Cs is now connected to thepositive and negative terminals of the amplifier 504. As a result, thevoltage differential across the positive and negative terminals of theamplifier 504 is now equal to the voltage across the sampling capacitorCs (based on the sensed leakage voltage during the PLL lock duration).Therefore, the amplifier 504 drives the gate voltage of transistor M1based on this sampled leakage voltage, which is representative of theleakage current of capacitor Cz during the PLL lock duration. Thus, acurrent matching the leakage current across the capacitor Cz during thePLL lock duration is supplied to the capacitor Cz (e.g., from supplyrail V_(DD)) when the PLL is not locked. In this manner, the leakagecurrent is sensed and supplied independent of the charge transferred bythe charge pump 402. In certain aspects, while the charge pump is off,the leakage voltage is stored on the sampling capacitor Cs at a ratethat is lower than a reference frequency (Fref) of the PLL and higherthan the PLL bandwidth (e.g., to ensure circuit stability).

During the sensing mode, the positive and negative terminals of theamplifier 504 are connected to a common-mode voltage (V_(CM)) (e.g., theswitch Φ₁ connecting the terminals together is closed) such that theamplifier 504 stays in a linear mode. Therefore, when the PLL is nolonger locked (e.g., switches Φ₁ are opened, and switches Φ_(1B) areclosed), the amplifier 504 can resume operations to control transistorM1 with reduced stabilization time. Moreover, during the sensing mode,the switch Φ_(1B) between the output of the amplifier 504 and the gateof transistor M1 is open. However, capacitor C_(H) coupled between thegate and source of transistor M1 maintains the gate-to-source voltage(V_(GS)) of transistor M1 such that the leakage compensation currentsupplied to the capacitor Cz continues even during the sensing mode(e.g., where the switches Φ_(1B) are open).

FIG. 6 is a circuit diagram of an example circuit 600 for leakagecurrent compensation using a capacitor having a leakage current that isrepresentative of the leakage current of filter capacitor Cz, inaccordance with certain aspects of the present disclosure. For example,the leakage circuitry 602 comprises a thin oxide capacitor Cz/n, whichhas a leakage current that is n times smaller than the leakage currentof the capacitor Cz. The capacitor Cz/n is coupled with a drain of PMOStransistor M2, which has a size n times smaller than the transistor M1(e.g., in certain aspects, n=10). An amplifier 604, the output of whichcontrols the gates of both transistors M1 and M2, may sense the leakagecurrent across the capacitor Cz/n, which is proportional to the leakageacross the filter capacitor Cz (e.g., by the ratio of 1/n). Therefore,the amplifier 604 drives the transistor M2 to compensate, or at leastadjust, for leakage across the capacitor Cz/n and drives the transistorM1 with the same voltage, which should compensate, or at least adjust,for the leakage in the capacitor Cz. That is, the current supplied to Czmay be n times greater than the leakage current of Cz/n (e.g., due tothe size ratio (n:1) of transistor M1 to transistor M2). The positiveterminal of the amplifier 604 may be coupled to one end of the capacitorCz/n, whereas the negative terminal of the amplifier 604 may be coupledto a common-mode voltage (V_(CM)) for the filter 404.

FIG. 7 is a circuit diagram of an example circuit 700 for leakagecurrent compensation using a representative capacitor Cz and a samplingcapacitor Cs, in accordance with certain aspects of the presentdisclosure. The leakage circuitry 702 includes a buffer 704 coupled toswitches Phi1. The buffer 704 is utilized in an effort to isolate theleakage sampling circuit from the filter capacitor Cz. During a sensingmode, switches Phi1 are closed, switch Phi1B is open, and the buffer 704charges capacitors Cz/n and Cs to a voltage approximately equal to thevoltage across the capacitor Cz. In certain aspects, the capacitor Cz/nis a thin oxide capacitor (e.g., having leakage proportional to leakageof the capacitor Cz by the capacitance ratio n), and the samplingcapacitor Cs is a thick oxide capacitor (e.g., having lower leakagecurrent than the thin oxide capacitor Cz). For example, the samplingcapacitor Cs may have a capacitance of 250 fF. In addition, during thesensing mode, switch Phi1B is open, and capacitor C_(H) maintains theV_(GS) of transistor M1. Therefore, the injection current fromtransistor M1 will continue during the sensing mode.

During the action mode, switches Phi1 are opened, and switch Phi1B isclosed. Thus, buffer 704 is decoupled from and no longer chargescapacitors Cz/n and Cs. As a result, the voltage across the capacitorCz/n will drop at a faster rate than the voltage across the capacitorCs, due to the higher leakage of Cz/n (because capacitor Cz/n is a thinoxide capacitor and Cs is a thick oxide capacitor). Therefore, thevoltage difference between capacitors Cz/n and Cs, caused in large partby the leakage of capacitor Cz/n, is representative of the leakage ofcapacitor Cz, which is also a thin oxide capacitor.

Thus, during the action mode, amplifier 706 drives the transistors M1and M2 based on a difference between the voltages across the capacitorsCz/n and Cs, which is representative of the leakage of capacitor Cz/n.The leakage of capacitor Cz/n will be proportional, by a ratio of 1/n,to the leakage of capacitor Cz. Therefore, by driving the transistor M1(e.g., having an area that is n times greater than that of thetransistor M2), the leakage current across capacitor Cz may becompensated. In certain aspects, the update rate (e.g., rate at whichthe voltage of capacitor Cz is sampled) may be greater than the PLLbandwidth and less than the reference frequency of the PLL.

In certain aspects, the amplifier 706 may be an operationaltransconductance amplifier (OTA) having a PMOS input and an operatingrange greater than 1 V (e.g., 1.8 V). The leakage compensation loop maybe stable without the addition of any compensation capacitors. Using athin oxide capacitor in the filter according to aspects of the presentdisclosure may save 40% area for PLL circuitry as compared to usingthick oxide capacitors. Moreover, aspects of the present disclosure mayreduce leaker current (e.g., better charge pump phase noise, therebylowering the spur). In certain aspects, noise may be filtered by therelatively large Cz capacitor.

In certain aspects, a compensation circuit may be provided that samplesthe voltage of the capacitor Cz if the Vtune (VC2) of the VCO reaches acertain threshold. That is, the voltage of the capacitor Cz may not besampled when the PLL is locked (e.g., charge pump is off) because thevoltage of the capacitor Cz may not change significantly in thiscondition.

In certain aspects, the leakage current of the capacitor Cz may besampled when Vtune (i.e., VC2) changes sufficiently (e.g., correspondingto a change in voltage across capacitor Cz). For example, comparatorsmay be used to compare Vtune or the capacitor Cz voltage with a numberof thresholds (e.g., 16 thresholds may be used). The greater the numberof thresholds, the greater resolution there may be in determining achange in the capacitor Cz voltage or Vtune. The leakage circuitry 702may sample the capacitor Cz voltage based on a determination that thisvoltage has changed sufficiently (e.g., based on the comparison of thecapacitor Cz voltage with the threshold voltages). By sampling thecapacitor Cz voltage after this voltage changes sufficiently, thesampling circuitry can be off during a portion of the time when the PLLis working to enter a locked condition. However, this introduces atradeoff between accuracy and the number of times the leakage current issampled. While most of the leakage current of the capacitor Cz may becompensated by the leakage circuitry, a remaining portion may becompensated by a leaker used for the charge pump linearity, for example.

FIG. 8 is a flow diagram of example operations 800 for leakage currentcompensation, or at least adjustment, in accordance with certain aspectsof the present disclosure. The operations 800 may be performed, forexample, by a circuit, such as the circuits 500, 700 for leakage currentcompensation illustrated in FIGS. 5 and 7.

The operations 800 may begin, at block 802, with the circuit determininga leakage voltage based on a leakage current of a capacitor (e.g., Cz)in a filter for a phase-locked loop (PLL). The capacitor may be a thinoxide capacitor, for example. The determining at block 802 may involveclosing a set of switches (e.g., switches Φ₁ or Phi1) for discontinuoussampling of the leakage voltage. At block 804, the circuit may generatea sourced current approximately equal to the leakage current, based onthe sampled leakage voltage. At block 806, an element of the circuit mayinject the sourced current into the capacitor.

According to certain aspects, the injecting at block 806 involvesinjecting the sourced current into the capacitor such that a voltagedrop across a resistor (e.g., Rz) in series with the capacitor isapproximately zero volts (0 V). A first end of the capacitor may becoupled to a reference node (e.g., electrical ground) for the filter,and a second end of the capacitor may be coupled to a first end of theresistor and to a current source configured to generate the sourcedcurrent. A second end of the resistor may be coupled to a charge pump(e.g., charge pump 402) of the PLL.

According to certain aspects, the sampled leakage voltage is equal to avoltage potential generated by the leakage current of the capacitorpassing through the resistor in series with the capacitor, as in FIG. 5.For other aspects, the sampled leakage voltage is equal to a voltagepotential generated by the leakage current of the capacitor passingthrough a series equivalent resistance (R_(eq)) of the capacitor, as inFIG. 7.

According to certain aspects, generating the sourced current at block804 entails controlling a current source with an amplifier (e.g.,amplifier 504 or 706) based on the sampled leakage voltage. For certainaspects, the current source comprises a transistor (e.g., M1). In thiscase, an output of the amplifier may be coupled to a gate of thetransistor, a source of the transistor may be coupled to a power supplyrail, and a drain of the transistor may be coupled to the capacitor.

According to certain aspects, the determining at block 802 involvesclosing the set of switches to store the leakage voltage across asampling capacitor (e.g., Cs) and to short first and second inputs ofthe amplifier to a common-mode voltage (V_(CM)) of the filter. Incertain aspects, the current source comprises a transistor (e.g., M1).In this case, the controlling at block 804 may entail closing anotherset of switches (e.g., switches Φ_(1B)) to sense the leakage voltagestored across the sampling capacitor with the first and second inputs ofthe amplifier and to connect an output of the amplifier with a gate ofthe transistor. In certain aspects, the set of switches is closed if acharge pump (e.g., charge pump 402) of the PLL is inactive, and theother set of switches is closed if the charge pump of the PLL is active.In certain aspects, another capacitor (e.g., C_(H)) is connected betweena source and a gate of the transistor and is configured to maintain agate-to-source voltage (V_(GS)) of the transistor if the other set ofswitches is open. In certain aspects, the capacitor may be a thin oxidecapacitor, and the sampling capacitor may be a thick oxide capacitor.

According to certain aspects, the determining at block 802 may includebuffering the leakage voltage with a voltage follower (e.g., buffer 704)and closing the set of switches to store the buffered leakage voltageacross a sampling capacitor (e.g., Cs) and across another capacitor(e.g., Cz/n) having a leakage current proportional to the leakagecurrent of the capacitor in the filter. For certain aspects, the currentsource comprises a first transistor (e.g., M1). The other capacitor maybe the same capacitor type as the capacitor in the filter. A first inputof the amplifier may be coupled to the other capacitor and to a drain ofa second transistor, and a second input of the amplifier may be coupledto the sampling capacitor. In this case, an output of the amplifier maybe coupled to a gate of the second transistor. A capacitance ratio (n)of the capacitor to the other capacitor may be equal to a size ratio ofthe first transistor to the second transistor.

In certain aspects, the controlling at block 804 includes closinganother set of switches (e.g., switches Phi1B) to connect the output ofthe amplifier with a gate of the first transistor and driving the gateof the first transistor and the gate of the second transistor with theamplifier. In certain aspects, the determining at block 802 furtherinvolves opening the other set of switches to disconnect the output ofthe amplifier from the gate of the first transistor. In this case, thecontrolling at block 804 may further entail opening the set of switchesto disconnect an output of the voltage follower from the other capacitorand from the sampling capacitor. In certain aspects, the set of switchesis closed if a charge pump of the PLL is inactive, and the other set ofswitches is closed if the charge pump is active. In certain aspects, yetanother capacitor (e.g., C_(H)) is connected between a source and a gateof the first transistor to maintain a gate-to-source voltage of thefirst transistor if the other set of switches is open. In certainaspects, the capacitor in the filter and the other capacitor may be thinoxide capacitors, and the sampling capacitor may be a thick oxidecapacitor.

According to certain aspects, the determining at block 802 may involveopening another set of switches (e.g., switches Φ_(1B) or Phi1B) for thediscontinuous sampling of the leakage voltage.

The various operations or methods described above may be performed byany suitable means capable of performing the corresponding functions.The means may include various hardware and/or software component(s)and/or module(s), including, but not limited to a circuit, anapplication specific integrated circuit (ASIC), or processor. Generally,where there are operations illustrated in figures, those operations mayhave corresponding counterpart means-plus-function components withsimilar numbering.

For example, means for transmitting may comprise a transmitter (e.g.,the transceiver front end 254 of the user terminal 120 depicted in FIG.2 or the transceiver front end 222 of the access point 110 shown in FIG.2) and/or an antenna (e.g., the antennas 252 ma through 252 mu of theuser terminal 120 m portrayed in FIG. 2 or the antennas 224 a through224 ap of the access point 110 illustrated in FIG. 2). Means forreceiving may comprise a receiver (e.g., the transceiver front end 254of the user terminal 120 depicted in FIG. 2 or the transceiver front end222 of the access point 110 shown in FIG. 2) and/or an antenna (e.g.,the antennas 252 ma through 252 mu of the user terminal 120 m portrayedin FIG. 2 or the antennas 224 a through 224 ap of the access point 110illustrated in FIG. 2). Means for processing or means for determiningmay comprise a processing system, which may include one or moreprocessors, such as the RX data processor 270, the TX data processor288, and/or the controller 280 of the user terminal 120 illustrated inFIG. 2.

Means for determining a leakage voltage and means for controlling maycomprise an amplifier, such as the amplifiers 408, 504, 604, and 706 ofFIGS. 4-7. Additionally or alternatively, means for determining theleakage voltage may comprise a sampling capacitor, such as samplingcapacitor Cs shown in FIGS. 5 and 7, and/or one or more sets of switches(e.g., switches Φ₁ and/or Φ_(m) depicted in FIG. 5 or switches Phi1and/or Phi1B depicted in FIG. 7). Means for sourcing current and meansfor injecting current may comprise a current source (e.g., a transistor,such as transistor M1 illustrated in FIGS. 4-7). Additionally oralternatively, means for injecting current may comprise a wire or traceconnected to (or close to) a terminal of a capacitor, such as filtercapacitor Cz, as portrayed in FIGS. 5 and 7.

As used herein, the term “determining” encompasses a wide variety ofactions. For example, “determining” may include calculating, computing,processing, deriving, investigating, looking up (e.g., looking up in atable, a database or another data structure), ascertaining and the like.Also, “determining” may include receiving (e.g., receiving information),accessing (e.g., accessing data in a memory) and the like. Also,“determining” may include resolving, selecting, choosing, establishingand the like.

As used herein, a phrase referring to “at least one of” a list of itemsrefers to any combination of those items, including single members. Asan example, “at least one of: a, b, or c” is intended to cover a, b, c,a-b, a-c, b-c, and a-b-c, as well as any combination with multiples ofthe same element (e.g., a-a, a-a-a, a-a-b, a-a-c, a-b-b, a-c-c, b-b,b-b-b, b-b-c, c-c, and c-c-c or any other ordering of a, b, and c).

The various illustrative logical blocks, modules and circuits describedin connection with the present disclosure may be implemented orperformed with a general purpose processor, a digital signal processor(DSP), an application specific integrated circuit (ASIC), a fieldprogrammable gate array (FPGA) or other programmable logic device (PLD),discrete gate or transistor logic, discrete hardware components, or anycombination thereof designed to perform the functions described herein.A general-purpose processor may be a microprocessor, but in thealternative, the processor may be any commercially available processor,controller, microcontroller, or state machine. A processor may also beimplemented as a combination of computing devices, e.g., a combinationof a DSP and a microprocessor, a plurality of microprocessors, one ormore microprocessors in conjunction with a DSP core, or any other suchconfiguration.

The methods disclosed herein comprise one or more steps or actions forachieving the described method. The method steps and/or actions may beinterchanged with one another without departing from the scope of theclaims. In other words, unless a specific order of steps or actions isspecified, the order and/or use of specific steps and/or actions may bemodified without departing from the scope of the claims.

The functions described may be implemented in hardware, software,firmware, or any combination thereof. If implemented in hardware, anexample hardware configuration may comprise a processing system in awireless node. The processing system may be implemented with a busarchitecture. The bus may include any number of interconnecting busesand bridges depending on the specific application of the processingsystem and the overall design constraints. The bus may link togethervarious circuits including a processor, machine-readable media, and abus interface. The bus interface may be used to connect a networkadapter, among other things, to the processing system via the bus. Thenetwork adapter may be used to implement the signal processing functionsof the physical (PHY) layer. In the case of a user terminal 120 (seeFIG. 1), a user interface (e.g., keypad, display, mouse, joystick, etc.)may also be connected to the bus. The bus may also link various othercircuits such as timing sources, peripherals, voltage regulators, powermanagement circuits, and the like, which are well known in the art, andtherefore, will not be described any further.

The processing system may be configured as a general-purpose processingsystem with one or more microprocessors providing the processorfunctionality and external memory providing at least a portion of themachine-readable media, all linked together with other supportingcircuitry through an external bus architecture. Alternatively, theprocessing system may be implemented with an ASIC (Application SpecificIntegrated Circuit) with the processor, the bus interface, the userinterface in the case of an access terminal), supporting circuitry, andat least a portion of the machine-readable media integrated into asingle chip, or with one or more FPGAs (Field Programmable Gate Arrays),PLDs (Programmable Logic Devices), controllers, state machines, gatedlogic, discrete hardware components, or any other suitable circuitry, orany combination of circuits that can perform the various functionalitydescribed throughout this disclosure. Those skilled in the art willrecognize how best to implement the described functionality for theprocessing system depending on the particular application and theoverall design constraints imposed on the overall system.

It is to be understood that the claims are not limited to the preciseconfiguration and components illustrated above. Various modifications,changes and variations may be made in the arrangement, operation anddetails of the methods and apparatus described above without departingfrom the scope of the claims.

What is claimed is:
 1. A circuit comprising: a first capacitor; a firsttransistor having a drain coupled to the first capacitor; an amplifier;a second capacitor; a first set of switches selectively coupled betweenthe first capacitor and the second capacitor; and a second set ofswitches selectively coupled between an output of the amplifier and agate of the first transistor.
 2. The circuit of claim 1, wherein thefirst capacitor is a different capacitor type than the second capacitor.3. The circuit of claim 1, wherein the first capacitor comprises a thinoxide capacitor and wherein the second capacitor comprises a thick oxidecapacitor.
 4. The circuit of claim 1, further comprising a thirdcapacitor coupled between a source and the gate of the first transistorand configured to maintain a gate-to-source voltage of the firsttransistor when the second set of switches is open.
 5. The circuit ofclaim 1, further comprising a resistor coupled in series with the firstcapacitor, wherein: the first set of switches is selectively coupledbetween a first terminal of the resistor and a first terminal of thesecond capacitor and is selectively coupled between a second terminal ofthe resistor and a second terminal of the second capacitor; and thesecond terminal of the resistor is coupled in series with the firstcapacitor and is coupled to the drain of the first transistor.
 6. Thecircuit of claim 5, wherein the second set of switches is selectivelycoupled between the first terminal of the second capacitor and a firstinput of the amplifier and is selectively coupled between the secondterminal of the second capacitor and a second input of the amplifier. 7.The circuit of claim 6, wherein the first set of switches is selectivelycoupled between inputs of the amplifier and a common-mode voltage node.8. The circuit of claim 7, wherein the first set of switches isconfigured to be closed for the circuit to: store, across the secondcapacitor, a leakage voltage based on a leakage current of the firstcapacitor; and short the first and second inputs of the amplifier to thecommon-mode voltage node.
 9. The circuit of claim 8, wherein the secondset of switches is configured to be closed for the circuit to: sense theleakage voltage stored across the second capacitor with the first andsecond inputs of the amplifier; and connect the output of the amplifierwith the gate of the first transistor.
 10. The circuit of claim 1,further comprising a second transistor having a gate coupled to theoutput of the amplifier and to the gate of the first transistor; and athird capacitor coupled to a first input of the amplifier and to a drainof the second transistor, wherein the second capacitor is coupled to asecond input of the amplifier.
 11. The circuit of claim 10, wherein thethird capacitor has a leakage current proportional to a leakage currentof the first capacitor.
 12. The circuit of claim 10, wherein the thirdcapacitor is the same capacitor type as the first capacitor.
 13. Thecircuit of claim 10, wherein the first capacitor and the third capacitorcomprise thin oxide capacitors.
 14. The circuit of claim 10, wherein acapacitance ratio of the first capacitor to the third capacitor is equalto a size ratio of the first transistor to the second transistor. 15.The circuit of claim 10, wherein the second set of switches isselectively coupled between the gate of the first transistor and thegate of the second transistor.
 16. The circuit of claim 10, furthercomprising a buffer having an input coupled to the first capacitor,wherein the first set of switches is selectively coupled between anoutput of the buffer and the third capacitor and is selectively coupledbetween the output of the buffer and the second capacitor.
 17. Thecircuit of claim 16, wherein: the buffer is configured to buffer aleakage voltage based on a leakage current of the first capacitor; andthe first set of switches is configured to be closed for the circuit tostore the buffered leakage voltage across the second capacitor andacross the third capacitor.
 18. The circuit of claim 17, wherein thesecond set of switches is configured, when opened, to disconnect theoutput of the amplifier from the gate of the first transistor andwherein the first set of switches is configured, when opened, todisconnect the output of the buffer from the second capacitor and fromthe third capacitor.
 19. The circuit of claim 1, wherein the first setof switches is configured to be closed for the circuit to sample aleakage voltage based on a leakage current of the first capacitor. 20.The circuit of claim 19, wherein: the first transistor is configured tosource current for injection into the first capacitor; and the amplifieris configured to control the first transistor based on the sampledleakage voltage such that the sourced current is approximately equal tothe leakage current.
 21. The circuit of claim 20, further comprising aresistor coupled in series with the first capacitor, wherein the sourcedcurrent is injected into the first capacitor such that a voltage dropacross the resistor is approximately zero volts.
 22. A phase-locked loop(PLL) comprising the circuit of claim 1, wherein the first capacitor isa filter capacitor in a filter for the PLL.
 23. The circuit of claim 22,wherein the PLL further comprises a charge pump, wherein the first setof switches is configured to be closed when the charge pump is inactiveand wherein the second set of switches is configured to be closed whenthe charge pump is active.